Field of the Invention
The present invention relates to a bus arbitration apparatus (bus arbiter) for arbitrating rights of use of a bus used for transfer of data or other such purpose (hereinafter referred to as “bus rights”).
Description of the Related Art
A bus arbiter determines a bus master to which a bus right is to be given based on bus right requests received from a plurality of bus masters connected to the same bus. In this specification, an example in which such a bus arbiter is used for an image forming apparatus such as a digital copier is described. Note that, the bus master is a device for controlling data transfer on a bus, and examples thereof include a central processing unit (CPU) for controlling a system, a communication interface such as an IEEE 1394, and a direct memory access (DMA).
Some image forming apparatus equipped with an auto document feeder have a flow reading mode. In the flow reading mode, the image forming apparatus reads documents one by one by causing a system control unit including a CPU to stop an optical scanning unit for irradiating the document with light at a document reading position. The system control unit is connected to the same bus to which a document convey control unit for conveying the document to the document reading position is connected.
Further, a memory for storing document data obtained by reading the document is also connected to the same bus to which the system control unit is connected.
Therefore, a large amount of data is transferred through the bus when the document is read. As an operation speed of the image forming apparatus increases, a transfer amount of the data on the bus increases. The bus arbiter is effective for arbitration of bus rights in the case where the transfer amount increases as described above.
Japanese Patent Application Laid-Open No. 2007-95089 is an example of such a bus arbiter. In Japanese Patent Application Laid-Open No. 2007-95089, a scanner (optical scanning unit), a system control unit, a memory, and the like are connected to the same general-purpose bus. When the bus right request is received from the bus master having the highest priority, the bus arbiter temporarily lowers bus use frequencies of the other bus masters. This guarantees data transfer efficiency of the bus master having the highest priority.
In general, a data transfer function unit such as a DMA for performing the data transfer is connected to the bus as the bus master in order to reduce load on the system control unit while not reducing the processing speed.
In a configuration in which a plurality of bus masters including the system control unit and the data transfer function unit exist on the bus, it is important to arbitrate the bus rights that allow use of the bus when controlling an operation of the image forming apparatus.
In the invention disclosed in Japanese Patent Application Laid-Open No. 2007-95089, the transfer performed by the bus master having the highest priority is guaranteed, but if the bus right request is simultaneously received from the bus master having a lower priority, the data transfer performed by the bus master having a relatively lower priority is not guaranteed. Further, if the bus right request is continuously received from the bus master having a higher priority, the data transfer performed by the bus master having the lower priority is postponed. Therefore, for example, if the priority of the bus master that controls communications for driving a motor for conveying paper is low, it is difficult to rotate the motor at a constant speed, which causes a paper jam or the like. Therefore, it is necessary to efficiently guarantee the data transfer performed by all the bus masters.